The present invention relates generally to integrated circuit fabrication and, more particularly, to an integrated circuit construction by which the effect of capacitive currents across dielectric material between current conducting lines is eliminated or greatly reduced.
As critical dimensions in microelectronics devices shrink, the device speed becomes limited by capacitance across dielectric (or insulator) films. In traditional semiconductor processing technology, the conductive layers are insulated from one another by dielectrics such as silicon dioxide or silicon nitride. As the pitch (i.e., spacing) of the conductive layers is reduced, the conductors begin to communicate with one another via capacitive currents across the dielectric. This effect reduces the effective speed of the devices.
The effect of capacitance across insulator films is reduced as the dielectric constant (xe2x80x9ckxe2x80x9d) of the insulator is reduced. To reduce the effect of line capacitance, insulating materials with lower dielectric constants, so-called low-k materials, are being developed. The materials have a dielectric constant less than silicon dioxide (k=3.85), but greater than a vacuum (k=1) or air (k≈1). Use of such low-k materials results in substantial process penalties, however, because these materials are generally very different from the materials currently in use, requiring changes in the processes for forming the microelectronics devices.
The problems created by capacitive currents across the dielectric between current-carrying conductive lines have been addressed by others in the past. To date, however, there is no known satisfactory solution to the problem of intra-level dielectric capacitive coupling.
U.S. Pat. No. 5,814,555 is issued to Bandyopadhyay et al. is directed to a method which uses the topography of the fill process to form voids in the vertical direction. This method reduces inter-level dielectric capacitive coupling. In contrast to inter-level coupling, intra-level dielectric capacitive coupling is a more critical parameter for device speed. Moreover, the method disclosed in U.S. Pat. No. 5,814,555 is incompatible with dual damascene processing for the back end of line.
U.S. Pat. No. 5,783,864 issued to Dawson et al. is directed to a multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect. The method by which this multilevel interconnect structure is formed requires an additional deep ultraviolet lithography step to form the air gaps. This additional step is cost-prohibitive.
In U.S. Pat. No. 5,759,913 issued to Fulford, Jr. et al., the fill dielectric must provide a high aspect ratio for the fill to avoid subsequent deposition which will, in general, make the metal etch require a much thicker hard mask than is actually required for the metal etch if, in fact, a hard mask is used at all. This results in a reduction in the process window for metal lithography and etch. In addition, the method disclosed in U.S. Pat. No. 5,759,913 is not compatible with dual damascene processing without excessively difficult metal recess steps. Furthermore, this method requires deposition of a hygroscopic dielectric material, limiting the applicability of the method.
In U.S. Pat. No. 5,407,860 issued to Stoltz et al., a selective deposition is used to form air gaps around adjacent current-conducting lines. This selective deposition requires, for example, the application of polytetrafluoroethylene such as Teflon (a trademark of E. I. DuPont deNemours and Co., Inc. of Wilmington, Del.) material. The use of polytetrafluoroethylene or similar materials limits the compatibility of this step with further processing. The presence of such materials which are xe2x80x9cnonwettingxe2x80x9d also decreases the effective reduction in line coupling because the dielectric of this material is greater than air.
To overcome the shortcomings of known attempts to solve the problem of intra-level dielectric capacitive coupling, a new method for forming an integrated circuit is provided. An object of the present invention is to provide an improved method of formation and an improved integrated circuit that eliminate or greatly reduce the effect of capacitive currents across dielectric material between current-conducting lines. Yet another object of this invention is to avoid the need to deposit a hygroscopic dielectric material, thereby expanding the applicability of the method and device.
Another object is to provide a method and device compatible with dual damascene processing for the back end of line. A related object is to provide a method and device compatible with dual damascene processing without excessively difficult metal recess steps. An additional related object of the present invention is to avoid the use of polytetrafluoroethylene or similar materials that limit the compatibility of the method with further processing. It is still another object of the present invention to eliminate or at least minimize cost-prohibitive method steps.
To achieve these and other objects, and in view of its purposes, the present invention provides a method for forming an integrated circuit. The method according to the present invention includes the steps of providing a stud dielectric and patterning a metal layer on the stud dielectric. A liner material is deposited on surfaces of lines of the metal layer which face one another. Spaces between surfaces of the liner material which face one another are filled with a dielectric material that is chemically differentiated from the liner material. The liner material is removed to create air gaps between the dielectric material and the surfaces of the lines of the metal layer.
An integrated circuit, constructed in accordance with the method of the present invention, includes a stud dielectric layer, a metal layer having conductive lines on the stud dielectric, and dielectric material in spaces between surfaces of the conductive lines of the metal layer facing one another and spaced from the conductive lines of the metal layer by air gaps.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.